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FDG6318PZ
January 2003
FDG6318PZ
Dual P-Channel, Digital FET
General Description
These dual P-Channel logic level enhancement mode MOSFET are produced using Fairchild Semiconductor's especially tailored to minimize on-state resistance. This device has been designed especially for bipolar digital transistors and small signal MOSFETS
Features
* -0.5A, -20V. r DS(ON) = 780m (Max)@ VGS = -4.5 V rDS(ON) = 1200m (Max) @ V GS = -2.5 V
* Very low level gate drive requirements allowing direct operation in 3V circuits (V GS(TH) < 1.5V). * Gate-Source Zener for ESD ruggedness (>1.4kV Human Body Model). * Compact industry standard SC-70-6 surface mount package.
Applications
* Battery management
S G D D G
Pin 1
S 1 or 4
6 or 3 D 5 or 2 G 4 or 1 S
G 2 or 5
S
D 3 or 6
SC70-6
Symbol VDSS VGS
The pinouts are symmetrical; pin1 and pin 4 are interchangeable.
MOSFET Maximum Ratings TA=25C unless otherwise noted
Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TC = 25oC, VGS = - 4.5V) Continuous (TC = 100 C, VGS = - 2.5V) Pulsed PD TJ, TSTG ESD Power dissipation Derate above 25C Operating and Storage Temperature Electrostatic Discharge Rating MIL-STD-883D Human Body Model ( 100pF / 1500 )
o
Ratings -20 12 -0.5 -0.3 Figure 4 0.3 2.4 -55 to 150 1.4
Units V V A A W mW/oC
o
C
kV
Thermal Characteristics
RJA Thermal Resistance Junction to Ambient (Note 1) 415
o
C/W
Package Marking and Ordering Information
Device Marking .68 Device FDG6318PZ Package SC70-6 Reel Size 7" Tape Width 8 mm Quantity 3000
(c)2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
FDG6318PZ
Electrical Characteristics TA = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = -250A, VGS = 0V VGS = - 16V , VGS = 0V VGS = 12V , VGS = 0V -20 -3 10 V A A
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = -250A ID = -0.5A, VGS = -4.5V ID = -0.4A, VGS = -2.5V -0.65 -0.9 580 910 -1.5 780 1200 V m
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(-2.5) Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at -4.5V Total Gate Charge at -2.5V Gate to Source Gate Charge Gate to Drain "Miller" Charge VDS = -10V, VGS = 0V, f = 1MHz VGS = 0V to -4.5V VGS = 0V to -2.5V VDD = -10V ID = -0.5A Ig = 1.0mA 85.4 24.9 8.83 1.08 0.67 0.21 0.33 1.62 1.0 pF pF pF nC nC nC nC
Switching Characteristics (VGS = -4.5V)
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = -10V, ID = -0.5A VGS = -4.5V, RGS = 120 10 13 40 24 35 96 ns ns ns ns ns ns
Drain-Source Diode Characteristics
V SD trr QRR
Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the center drain pad. RJC is guaranteed by design while RCA is determined by user's board design. RJA = 415 oC/W when mounted on a 1inch2 copper pad.
Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge
ISD = -0.5A ISD = -0.5A, dISD/dt = 100A/s ISD = -0.5A, dISD/dt = 100A/s
-
-0.9 -
-1.2 22 16
V ns nC
(c)2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
FDG6318PZ
Typical Characteristic
1.2
TA = 25C unless otherwise noted
0.6
POWER DISSIPATION MULTIPLIER
1.0 -ID, DRAIN CURRENT (A) VGS = -4.5V 0.4
0.8
0.6
VGS = -2.5V 0.2
0.4
0.2
0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
0 25 50 75 100 125 150 TA, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJA, NORMALIZED
0.1
PDM
t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 0.01 10-5 10 -4 10-3 10-2 10-1 100 101 102 10 3 t , RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
20 TA = 25 oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125
10 -IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
1
VGS = -4.5V VGS = -2.5V
0.4 10-5 10 -4 10-3 10 -2 10-1 t, PULSE WIDTH (s) 100 10 1 102 103
Figure 4. Peak Current Capability
(c)2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
FDG6318PZ
Typical Characteristic (Continued) TA = 25C unless otherwise noted
10 3 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = -10V 2 TJ = 150oC TJ = 25oC
-ID, DRAIN CURRENT (A)
100s
1 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 SINGLE PULSE TJ = MAX RATED TA = 25oC
-ID, DRAIN CURRENT (A)
10ms
1
TJ = -55oC
0.05 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 30
0 0 1 2 3 4 -VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
3 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -ID, DRAIN CURRENT (A) TA = 25oC 2 VGS = -4.5V rDS(ON), DRAIN TO SOURCE ON RESISTANCE () 0.9 1.0
Figure 6. Transfer Characteristics
ID = -0.5A
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
0.8
VGS = -2.5V 1 VGS = -2V
0.7
ID = -0.1A
0.6
0 0 0.5 1.0 1.5 2.0 2.5 3.0 -VDS, DRAIN TO SOURCE VOLTAGE (V)
0.5 2 3 4 5 6 -VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs Gate Voltage and Drain Current
1.2
1.50 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE
VGS = VDS, I D = 250A
1.25
1.0
1.00
0.8
VGS = -4.5V, ID = -0.5A 0.75 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature
(c)2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
FDG6318PZ
Typical Characteristic (Continued) TA = 25C unless otherwise noted
1.10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 100 C, CAPACITANCE (pF) 1.05 COSS CDS + CGD 200 CISS = CGS + CGD
CRSS = C GD
1.00
10 VGS = 0V, f = 1MHz 0.95 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 5 0.1 1 -VDS , DRAIN TO SOURCE VOLTAGE (V) 10 20
Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 -VGS , GATE TO SOURCE VOLTAGE (V) VDD = -10V 8
Figure 12. Capacitance vs Drain to Source Voltage
6
4 WAVEFORMS IN DESCENDING ORDER: ID = -0.5A ID = -0.1A 0 0.5 1.0 Qg, GATE CHARGE (nC) 1.5 2.0
2
0
Figure 13. Gate Charge Waveforms for Constant Gate Currents
(c)2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
FDG6318PZ
PSPICE Electrical Model
.SUBCKT FDG6318PZ 2 1 3 ; CA 12 8 0.6e-10 CB 15 14 1.1e-10 CIN 6 8 0.75e-10 DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -23.3 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 0.47e-9 LSOURCE 3 7 0.47e-9
GATE 1 LGATE RGATE 9 RLGATE CIN 20
rev January 2003
ESG 10 8+ 6 5 RLDRAIN RSLC2 RSLC1 51 + 5 ESLC 51 50 DPLCAP EVTHRES + 19 8 6 MSTRO 8 RDRAIN 16 21 MMED MWEAK DBODY 11 + 17 18 LDRAIN DRAIN 2
EBREAK
EVTEMP 18 + 22
DBREAK LSOURCE RSOURCE 7 SOURCE 3 RLSOURCE
MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 280e-3 RGATE 9 20 12.4 RLDRAIN 2 5 10 RLGATE 1 9 4.7 RLSOURCE 3 7 4.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 190e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 13 8 S1B 13 CA + EGS 6 8 S2A 15 14 13 S2B
RBREAK 17 18 RVTEMP CB 14 IT 19 VBAT + 8 RVTHRES 22
+ EDS 5 8
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*20),2.5))} .MODEL DBODYMOD D (IS = 7.7e-11 N=1.277 RS = 1e-3 TRS1 = 2.8e-1 TRS2 = 3e-4 XTI=0 IKF=0.5 CJO = 3.9e-11 TT=33e-9 M = 0.50) .MODEL DBREAKMOD D (RS = 5.3e-1 TRS1 = 5.5e-3 TRS2 = -9e-5) .MODEL DPLCAPMOD D (CJO = 0.5e-10 IS = 1e-30 N = 10 M = 0.55) .MODEL MMEDMOD PMOS (VTO = -1.17 KP = 0.6 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 12.4) .MODEL MSTROMOD PMOS (VTO = -1.45 KP = 1.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD PMOS (VTO = -0.99 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 124 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 5.5e-4 TC2 = -1e-7) .MODEL RDRAINMOD RES (TC1 = 2.8e-3 TC2 = 4.9e-6) .MODEL RSLCMOD RES (TC1 = 3.7e-3 TC2 = 7.8e-6) .MODEL RSOURCEMOD RES (TC1 = 3e-3 TC2 = 5.2e-6) .MODEL RVTHRESMOD RES (TC1 = 9e-4 TC2 = 3e-7) .MODEL RVTEMPMOD RES (TC1 = -5.5e-4 TC2 = -1e-9) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = 0.5 VOFF= 0.2) VON = 0.2 VOFF= 0.5) VON = 0.4 VOFF= -0.1) VON = -0.1 VOFF= 0.4)
(c)2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
FDG6318PZ
SABER Electrical Model
REV January 2003 template FDG6318PZ n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 7.7e-11, nl=1.277, rs = 1e-3, trs1 = 2.8e-1, trs2 = 3e-4, xti=0, cjo = 3.9e-11, ikf=0.5, tt = 33e-9, m = 0.50) dp..model dbreakmod = (rs = 5.3e-1, trs1 = 5.5e-3, trs2 = -9.0e-5) dp..model dplcapmod = (cjo = 0.5e-10, isl=10e-30, nl=10, m=0.55) m..model mmedmod = (type=_p, vto = -1.17, kp=0.6, is=1e-30, tox=1) m..model mstrongmod = (type=_p, vto = -1.45, kp = 1.5, is = 1e-30, tox = 1) m..model mweakmod = (type=_p, vto = -0.99, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0.2) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = 0.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.4, voff = -0.1) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.4)
ESG LDRAIN + 5 RLDRAIN RSLC2 RSLC1 51 ISCL 50 DPLCAP EVTHRES + 19 8 6 MSTRO CIN 8 RDRAIN 16 21 MMED DBREAK LSOURCE RSOURCE 7 SOURCE 3 RLSOURCE S1A S2A res.rbreak n17 n18 = 1, tc1 = 5.5e-4, tc2 = -1e-7 15 14 13 res.rdrain n50 n16 = 280e-3, tc1 = 2.8e-3, tc2 = 4.9e-6 12 8 13 res.rgate n9 n20 = 12.4 S1B S2B res.rldrain n2 n5 = 10 13 CB res.rlgate n1 n9 = 4.7 CA 14 + res.rlsource n3 n7 = 4.7 + 6 res.rslc1 n5 n51= 1e-6, tc1 = 3.7e-3, tc2 =7.8e-6 EDS 5 EGS 8 8 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 190e-3, tc1 = 3e-3, tc2 =5.2e-6 res.rvtemp n18 n19 = 1, tc1 = -5.5e-4, tc2 = -1e-9 res.rvthres n22 n8 = 1, tc1 = 9e-4, tc2 = 3e-7 RBREAK 17 18 RVTEMP IT 19 VBAT + 8 RVTHRES 22 MWEAK DBODY 11 EBREAK + 17 18 DRAIN 2
c.ca n12 n8 = 0.6e-10 c.cb n15 n14 = 1.1e-10 c.cin n6 n8 = 0.75e-10 dp.dbody n5 n7 = model=dbodymod dp.dbreak n7 n11 = model=dbreakmod dp.dplcap n10 n6 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 0.47e-9 l.lsource n3 n7 = 0.47e-9
LGATE GATE 1 RLGATE RGATE 9 20
10
8 6
EVTEMP 18 + 22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
spe.ebreak n5 n11 n17 n18 = -23.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n5 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/20))** 2.5)) } }
(c)2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
FDG6318PZ
SPICE Thermal Model
REV January 2003 FDG6318PZ_JA Junction Ambient Copper Area= 1sq.in CTHERM1 Junction c2 0.17e-4 CTHERM2 c2 c3 2.7e-4 CTHERM3 c3 c4 5.5e-4 CTHERM4 c4 c5 1.4e-3 CTHERM5 c5 c6 2.2e-3 CTHERM6 c6 c7 2.6e-3 CTHERM7 c7 c8 6.6e-3 CTHERM8 c8 Ambient 0.29 RTHERM1 Junction c2 11.2 RTHERM2 c2 c3 11.5 RTHERM3 c3 c4 12.5 RTHERM4 c4 c5 27 RTHERM5 c5 c6 81 RTHERM6 c6 c7 88 RTHERM7 c7 c8 92 RTHERM8 c8 Ambient 93
th JUNCTION
RTHERM1 8
CTHERM1
RTHERM2 7
CTHERM2
RTHERM3 6
CTHERM3
RTHERM4 5
CTHERM4
SABER Thermal Model
SABER thermal model FDG6318PZ Copper Area= 1sq.in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th c2 = 0.17e-4 ctherm.ctherm2 c2 c3 = 2.7e-4 ctherm.ctherm3 c3 c4 = 5.5e-4 ctherm.ctherm4 c4 c5 = 1.4e-3 ctherm.ctherm5 c5 c6 = 2.2e-3 ctherm.ctherm6 c6 c7 = 2.6e-3 ctherm.ctherm7 c7 c8 = 6.6e-3 ctherm.ctherm8 c8 tl = 0.29 rtherm.rtherm1 th c2 = 11.2 rtherm.rtherm2 c2 c3 = 11.5 rtherm.rtherm3 c3 c4 = 12.5 rtherm.rtherm4 c4 c5 = 27 rtherm.rtherm5 c5 c6 = 81 rtherm.rtherm6 c6 c7 = 88 rtherm.rtherm7 c7 c8 = 92 rtherm.rtherm8 c8 tl = 93 }
RTHERM5
CTHERM5 4
RTHERM6 3
CTHERM6
RTHERM7 2
CTHERM7
RTHERM8
CTHERM8
tl
AMBIENT
(c)2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev.B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
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SPMTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TruTranslationTM UHCTM UltraFET(R) VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I2

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